HD6417706 Datasheet, PDF (553/709 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

1. Scan mode is selected (MULTI = 1, SCN = 1), channel group 0 is selected (CH2 = 0), analog
input channels AN0 to AN2 are selected (CH1 = 1, CH0 = 0), and A/D conversion is started
(ADST = 1).
2. When A/D conversion of the first channel (AN0) is completed, the result is transferred into
ADDRA. Next, conversion of the second channel (AN1) starts automatically.
3. Conversion proceeds in the same way through the third channel (AN2).
4. When conversion of all the selected channels (AN0 to AN2) is completed, the ADF flag is set
to 1 and conversion of the first channel (AN0) starts again. If the ADIE bit is set to 1, an ADI
interrupt is requested at this time.
5. Steps 2 to 4 are repeated as long as the ADST bit remains set to 1. When the ADST bit is
cleared to 0, A/D conversion stops. After that, if the ADST bit is set to 1, A/D conversion
starts again from the first channel (AN0).
ADST
ADF
Channel 0 (AN₀)
operating
Channel 1 (AN₁)
operating
Channel 2 (AN₂)
operating
Channel 3 (AN₃)
operating
ADDRA*²
ADDRB*²
ADDRC*²
Set*¹
Continuous A/D conversion
Clear*¹
Clear*¹
Waiting
Waiting
Waiting
Waiting
A/D conversion 1
Waiting
A/D conversion 2
A/D conversion 4
Waiting
A/D conversion 5
A/D conversion 3
Waiting
Waiting
Waiting
Transfer
A/D conversion result 1
A/D conversion result 4
A/D conversion result 2
A/D conversion result 3
ADDRD*²
Notes: 1. Downward arrows indicate instruction executed by software.
2. Data is ignored during conversion.
Figure 19.7 Example of A/D Converter Operation (Scan Mode,
Channels AN0 to AN2 Selected)
Rev. 4.00, 03/04, page 507 of 660