HD6417706 Datasheet, PDF (250/709 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

However, the WAIT signal is ignored in the following cases:
• In 16-byte DMA transfer or dual addressing mode, or when writing data to the external address
area
• In 16-byte DMA transfer or single addressing mode, or when transferring data from an
external device with DACK to the external address area
• When accessing cache for write back
Wait states inserted
by WAIT signal
T1
Tw
Tw
Tw
T2
CKIO
A25 to A0
CSn
RD/WR
Read
RD
D31 to D0
Write
WEn
D31 to D0
WAIT
BS
Figure 8.10 Basic Interface Wait State Timing (Wait State Insertion by WAIT Signal
WAITSEL = 1)
Rev. 4.00, 03/04, page 204 of 660