HD6417706 Datasheet, PDF (206/709 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

• Refresh function
 Refresh cycles will be automatically maintained in the sleep mode even after the external
bus frequency is reduced to 1/4 of its normal operating frequency
• The refresh counter can be used as an interval timer
 Outputs an interrupt request signal using the compare-matching function
 Outputs an interrupt request signal when the refresh counter overflows
, to ,
,
Wait
controller
Area
controller
WCR1
WCR2
Bus
interface
BCR1
RD/
to
CKE
,
Memory
controller
BCR2
MCR
PCR
Interrupt
controller
Refresh
controller
RFCR
RTCNT
Comparator
RTCOR
RTCSR
Legend
WCR: Wait state control register
BCR : Bus control register
MCR : Memory control register
PCR : PCMCIA control register
BSC
RFCR : Refresh count register
RTCNT: Refresh timer count register
RTCOR: Refresh time constant register
RTCSR: Refresh timer control/status register
Figure 8.1 BSC Functional Block Diagram
Rev. 4.00, 03/04, page 160 of 660