HD6417706 Datasheet, PDF (637/709 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

24.3.6 Synchronous DRAM Timing
CKIO
A25 to A16
A12 or A11
A15 to A0
Tr
Tc1
Tc2
(Tpc)
t_AD
Row address
t_AD
t_AD
Row address
t_AD
t_AD
Row address
t_CSD3
;;;;tAD
t_AD
Read A
command
t_AD
Column address
t_CSD3
RD/
t_RWD
t_RASD
t_RASD
t_RWD
t_CASD
t_CASD
DQMxx
D31 to D0
t_DQMD
t_DQMD
t_RDS2 t_RDH2
t_BSD
t_BSD
CKE
DACKn
t_DAKD1
(High)
t_DAKD1
Figure 24.22 Synchronous DRAM Read Bus Cycle (RCD = 0, CAS Latency = 1, TPC = 0)
Rev. 4.00, 03/04, page 591 of 660