HD6417706 Datasheet, PDF (120/709 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

3.5.5
Processing Flow in Event of MMU Exception (Same Processing Flow for CPU
Address Error)
Figure 3.11 shows the MMU exception signals in the instruction fetch mode.
IF ID EX MA WB
ID EX MA WB
ID EX MA WB
NOP
NOP
MMU exception handler
IF
ID
Handler transition
processing
EX MA WB
: Exception source stage
IF
ID
EX
MA
WB
NOP
= Instruction fetch
= Instruction decode
= Instruction execution
= Memory access
= Write back
= No operation
Figure 3.11 MMU Exception Signals in Instruction Fetch
Rev. 4.00, 03/04, page 74 of 660