HD6417706 Datasheet, PDF (215/709 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

8.4 Register Description
The BSC has 11 registers. The synchronous DRAM also has a built-in synchronous DRAM mode
register. These registers control direct connection interfaces to memory, wait states and refreshes.
Refer to section 23, List of Registers, for more details of the addresses and access sizes.
• Bus control register 1 (BCR1)
• Bus control register 2 (BCR2)
• Wait state control register 1 (WCR1)
• Wait state control register 2 (WCR2)
• Individual memory control register (MCR)
• PCMCIA control register (PCR)
• Synchronous DRAM mode register (SDMR)
• Refresh timer control/status register (RTCSR)
• Refresh timer counter (RTCNT)
• Refresh time constant register (RTCOR)
• Refresh count register (RFCR)
8.4.1 Bus Control Register 1 (BCR1)
Bus control register 1 (BCR1) is a 16-bit read/write register that sets the functions and bus cycle
state for each area. It is initialized to H'0000 by a power-on reset, but is not initialized by a manual
reset or by standby mode. Do not access external memory outside area 0 until BCR1 register
initialization is complete.
Bit
Bit Name Initial Value R/W Description
15
PULA
0
R/W Pin A25 to A0 Pull-Up
Specifies whether or not pins A25 to A0 are pulled up
for 4 cycles immediately after BACK is asserted.
0: Not pulled up
1: Pulled up
14
PULD
0
R/W Pin D31 to D0 Pull-Up
Specifies whether or not pins D31 to D0 are pulled up
when not in use.
0: Not pulled up
1: Pulled up
Rev. 4.00, 03/04, page 169 of 660