HD6417706 Datasheet, PDF (447/709 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

Section 15 Smart Card Interface
As an added serial communications interface function, the SCI supports an IC card (smart card)
interface that conforms to the data transfer protocol (asynchronous half-duplex character
transmission protocol) of the ISO/IEC standard 7816-3 for identification of cards. Register settings
are used to switch between the ordinary serial communication interface and the smart card
interface. Figure 15.1 is the block diagram of the smart card interface.
15.1 Feature
The smart card interface has the following features:
• Asynchronous mode
 Data length: Eight bits
 Parity bit generation and check
 Receive mode error signal detection (parity error)
 Transmit mode error signal detection and automatic re-transmission of data
 Supports both direct convention and inverse convention
• Bit rate can be selected using on-chip baud rate generator.
• Three types of interrupts: Transmit-data-empty, receive-data-full, and communication-error
interrupts are requested independently.
Module data bus
Internal
data bus
RxD0
TxD0
SCK0
SCRDR
SCRSR
SCTDR
SCTSR
SCSCMR
SCSSR
SCSCR
SCSMR
Transmit/
receive
control
SCBRR
Baud rate
generator
Parity generation
Parity check
Clock
External clock
Pφ
Pφ/4
Pφ/16
Pφ/64
Legend
SCSCMR: Smart card mode register
SCRSR: Receive shift register
SCRDR: Receive data register
SCTSR: Transmit shift register
SCTDR: Transmit data register
TXI
RXI
ERI
SCI
SCSMR: Serial mode register
SCSCR: Serial control register
SCSSR: Serial status register
SCBRR: Bit rate register
Figure 15.1 Smart Card Interface Block Diagram
Rev. 4.00, 03/04, page 401 of 660