HD6417706 Datasheet, PDF (434/709 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

Figure 14.16 shows an example of SCI receive operation using a multiprocessor format.
Start Data
1 _bit (ID1)
Serial
data
0 D0 D1
MPIE
Stop Start Data
MPB bit bit (data 1)
D7 1 1 0 D0 D1
Stop
MPB bit
1
D7 0 1
Idling
(marking)
RDRF
RDR
value
ID1
RXI interrupt request
(multiprocessor interrupt)
generated, MPIE = 0
Reads RDR data with
the RXI interrupt
processing routine
and clears RDRF bit to 0
ID is not station's
ID, so MPIE bit is
set to 1 again
No RXI interrupt,
generated
RDR state
is maintained
(a) Own ID does not matches data
Start Data
1 _bit (ID2)
Serial
data
0 D0 D1
Stop Start Data
MPB bit bit (Data 2)
D7 1 1 0 D0 D1
Stop
MPB bit
1
D7 0 1
Idling
(marking)
MPIE
RDRF
RDR
value
ID1
ID2
Data2
RXI interrupt
request
(multiprocessor
interrupt) generated,
MPIE = 0
Reads RDR data with
the RXI interrupt
processing routine
and clears
RDRF bit to 0
ID is that of station,
so reception
continues unchanged
and data is received
by the RXI interrupt
processing routine
(b) Own ID matches data
MPIE bit
set to 1
again
Figure 14.16 Example of SCI Receive Operation
Rev. 4.00, 03/04, page 388 of 660