HD6417706 Datasheet, PDF (401/709 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

Bit
Bit Name Initial Value R/W Description
2
MP
0
R/W Multiprocessor Mode
Selects multiprocessor format. When
multiprocessor format is selected, settings of the
PE and O/E bits are ignored. The MP setting is
used available in the asynchronous mode; it is
ignored in the clock synchronous mode. For the
multiprocessor communication function, see
section 14.4.2, Multiprocessor Communication.
0: Multiprocessor function disabled
1: Multiprocessor format selected
1
CKS1
0
R/W Clock Select 1 and 0
0
CKS0
0
R/W These bits select the internal clock source of the
on-chip baud rate generator. Four clock sources
are available. Pφ, Pφ/4, Pφ/16 and Pφ/64. For
further information on the clock source, bit rate
register settings, and baud rate, see section
14.3.10, Bit Rate Register (SCBRR).
00: Pφ
01: Pφ/4
10: Pφ/16
11: Pφ/64
Note: Pφ: Peripheral clock
14.3.6 Serial Control Register (SCSCR)
The serial control register (SCSCR) operates the SCI transmitter/receiver, selects the serial clock
output in the asynchronous mode, enables/disables interrupt requests, and selects the
transmit/receive clock source. The CPU can always read and write the SCSCR.
Bit
Bit Name Initial Value R/W Description
7
TIEs
0
R/W Transmit Interrupt Enable
Enables or disables the TXI request when the
serial transmit data is transferred from SCTDR to
SCTCR and the TDRE in SCSSR is set to 1.
0: Transmit-data-empty interrupt request (TXI) is
disabled
Note: The TXI interrupt request can be cleared by
reading TDRE after it has been set to 1, then
clearing TDRE to 0, or by clearing TIE to 0.
1: Transmit-data-empty interrupt request (TXI) is
enabled
Rev. 4.00, 03/04, page 355 of 660