HD6417706 Datasheet, PDF (364/709 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

12.3.5 Timer Counters 0 to 2 (TCNT_0 to TCNT_2)
TCNT counts down according to the input of a clock. The timer counters are 32-bit read/write
registers. The TMU has three timer counters, one for each channel.The clock input is selected
using the TPSC2 to TPSC0 bits in the TCR_0 to TCR_2.
When a TCNT count-down results in an underflow (H'00000000 → H'FFFFFFFF), the underflow
flag (UNF) in the timer control register (TCR) of the relevant channel is set. The TCOR value is
simultaneously set in TCNT itself and the count-down continues from that value.
Because the internal bus for this LSI on-chip supporting modules is 16 bits wide, a time lag can
occur between the time when the upper 16 bits and lower 16 bits are read. Since TCNT counts
sequentially, this time lag can create discrepancies between the data in the upper and lower halves.
To correct the discrepancy, a buffer register is connected to TCNT so that upper and lower halves
are not read separately. The entire 32-bit data in TCNT can thus be read at once.
TCNT is initialized to H'FFFFFFFF by a power-on reset or manual reset; it is not initialized in
standby mode, and retains its contents.
12.3.6 Input Capture Register 2 (TCPR_2)
The input capture register (TCPR_2) is a read-only 32-bit register built only into timer 2. Control
of TCPR_2 setting conditions due to the TCLK pin is affected by the input capture function bits
(ICPE1/ICPE2 and CKEG1/CKEG0) in TCR2. When a TCPR_2 setting indication due to the
TCLK pin occurs, the value of TCNT_2 is copied into TCPR_2.
TCNT_2 is not initialized by a power-on reset or manual reset, or in standby mode.
Rev. 4.00, 03/04, page 318 of 660