HD6417706 Datasheet, PDF (640/709 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

Tr Trw Tc1 Tc2 Tc3 Tc4/Td1 Td2 Td3 Td4 (Tpc)
CKIO
A25 to A16
A12 or A11
A15 to A0
t_AD
Row address
t_AD
t_AD
t_AD
t_AD t_AD
Row
; ;; _address
Read command
t_AD t_AD
t_AD
Row
address
;; ;;;; _tCSD3
Column address (1-4)
t_AD
t_CSD3
t_RWD
t_RWD
RD/
t_RASD
t_RASD
t_CASD
t_CASD
DQMxx
t_DQMD
D31 to D0
(read)
t_RDS2 t_RDH2
t_BSD
t_DQMD
t_RDS2 t_RDH2
t_BSD
CKE
DACKn
t_DAKD1
(High)
t_DAKD1
Figure 24.25 Synchronous DRAM Read Bus Cycle (Burst Read (Single Read × 4), RCD = 1,
CAS Latency = 3, TPC = 0)
Rev. 4.00, 03/04, page 594 of 660