HD6417706 Datasheet, PDF (489/709 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

Table 16.5 Maximum Bit Rates during External Clock Input (Asynchronous Mode)
Pφ (MHz)
8
9.8304
12
14.7456
16
19.6608
20
24
24.576
28.7
30
External Input Clock (MHz)
2.0000
2.4576
3.0000
3.6864
4.0000
4.9152
5.0000
6.0000
6.1440
7.1750
7.5000
Maximum Bit Rate (bit/s)
125000
153600
187500
230400
250000
307200
312500
375000
384000
448436
468750
16.3.9 FIFO Control Register 2 (SCFCR2)
The FIFO control register 2 (SCFCR2) resets the number of data in the SCFTDR2 and SCFRDR2,
sets the number of trigger data, and contains an enable bit for the loop back test. The SCFCR2 is
always read and written by the CPU.
Bit
Bit Name Initial Value R/W Description
7
RTRG1 0
R/W Trigger of the Number of Receive FIFO Data
6
RTRG0 0
R/W Set the reference number of the receive data full.
The RDF in SCSSR2 is set to 1, when the receiving
data count has exceeded the following trigger
number.
Trigger number of receive data.
00:
1
01:
4
10:
8
11:
14
Rev. 4.00, 03/04, page 443 of 660