HD6417706 Datasheet, PDF (104/709 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

3.2.5 MMU Control Register (MMUCR)
The MMU control register (MMUCR) makes the MMU settings. Any program that modifies
MMUCR should reside in the P1 or P2 area.
Bit
Bit Name Initial Value R/W Description
31 to 9 
All 0
R Reserved
These bits are always read as 0. The write value should
always be 0.
8
SV

R/W Single virtual memory mode
0: multiple virtual memory mode
1: single virtual memory mode
7, 6 
All 0
R Reserved
These bits are always read as 0. The write value should
always be 0.
5, 4 RC
All 0
R/W Random counter
A 2-bit random counter, automatically updated by
hardware according to the following rules in the event of
an MMU exception. When a TLB miss exception occurs,
all TLB entry ways corresponding to the virtual address at
which the exception occurred are checked, and if all ways
are valid, 1 is added to RO; if there is one or more invalid
ways, they are set by priority from way 0, in the order:
way 0, way 1, way 2, way 3. In the event of an MMU
exception other than a TLB miss exception, the way
which caused the exception is set in RC.
3

0
R Reserved
This bit is always read as 0. The write value should
always be 0.
2
TF
0
R/W TLB flush
When 1 is set, all valid bits of TLB are cleared to 0 (flush).
This bit is always reads as 0.
1
IX
0
R/W Index mode
When 0, VPN bits 16 to 12 are used as the TLB index
number. When 1, the value obtained by EX-ORing ASID
bits 4 to 0 in PTEH and VPN bits 16 to 12 are used as the
TLB index number.
0
AT
0
R/W Address translation
Enables (valid) or disables (invalid) the MMU.
0: MMU disabled
1: MMU enabled
Rev. 4.00, 03/04, page 58 of 660