HD6417706 Datasheet, PDF (555/709 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

Table 19.3 A/D Conversion Time (Single Mode)
CKS = 0
Symbol Min
Typ Max
Min
A/D conversion start tD
delay
17
—
28
10
Input sampling time
tSPL
—
129 —
—
A/D conversion time tCONV
514
—
525
259
Note: Values in the table are numbers of states (tcyc).
CKS = 1
Typ
Max
—
17
65
—
—
266
19.6.5 External Trigger Input Timing
A/D conversion can be externally triggered. When the TRGE1, TRGE0 bits in ADCR are set to 1.
external trigger input is enabled at the ADTRG pin. A high-to-low transition at the ADTRG pin
sets the ADST bit in ADCSR to 1, starting A/D conversion. Other operations, regardless of the
conversion mode, are the same as if the ADST bit had been set to 1 by software. Figure 19.9
shows the timing.
Pφ
External
trigger signal
ADST
A/D conversion
Figure 19.9 External Trigger Input Timing
19.7 Interrupt Requests
The A/D converter generates an interrupt (ADI) at the end of A/D conversion. The ADI interrupt
request can be enabled or disabled by the ADIE bit in ADCSR.
Rev. 4.00, 03/04, page 509 of 660