HD6417706 Datasheet, PDF (225/709 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

Table 8.7 Area 5 Wait Control
WCR2's bits
Bit 12: Bit 11: Bit 10:
A5W2 A5W1 A5W0
0
0
0
1
1
0
1
1
0
0
1
1
0
1
Description
First Cycle
Burst Cycle
(Excluding First Cycle)
Inserted
Wait States
WAIT Pin
Number of States
Per Data Transfer WAIT Pin
0
Ignored
2
Enable
1
Enable
2
Enable
2
Enable
3
Enable
3
Enable
4
Enable
4
Enable
4
Enable
6
Enable
6
Enable
8
Enable
8
Enable
10
Enable
10
Enable
Table 8.8 Area 4 Wait Control
Bit 9: A4W2
0
1
WCR2's bits
Bit 8: A4W1
0
1
0
1
Bit 7: A4W0
0
1
0
1
0
1
0
1
Description
Inserted Wait State WAIT Pin
0
Ignored
1
Enable
2
Enable
3
Enable
4
Enable
6
Enable
8
Enable
10
Enable
Rev. 4.00, 03/04, page 179 of 660