HD6417706 Datasheet, PDF (419/709 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

Table 14.8 Serial Mode Register Settings and SCI Communication Formats
Mode
Asynchronous
SCSMR Settings
Bit 7 Bit 6 Bit 5 Bit 2
C/A CHR PE MP
00
0
0
1
1
0
1
Asynchronous
0
*
1
(multiprocessor
*
format)
1
*
*
Clock
1*
*
*
synchronous
Note: * Don't care
Bit 3
STOP
0
1
0
1
0
1
0
1
0
1
0
1
*
SCI Communication Format
Data Parity Multipro- Stop Bit
Length Bit
cessor Bit Length
8-bit
Not set Not set 1 bit
2 bits
Set
1 bit
2 bits
7-bit
Not set
1 bit
2 bits
Set
1 bit
2 bits
8-bit
Not set Set
1 bit
2 bits
7-bit
1 bit
2 bits
8-bit
Not set None
Table 14.9 SCSMR and SCSCR Settings and SCI Clock Source Selection
SCSMR
Mode
Bit 7 C/A
Asynchronous 0
mode
SCSCR
Settings
Bit 1 Bit 0
CKE1 CKE0
0
0
1
Clock
1
synchronous
mode
1
0
1
0
0
1
1
0
1
SCI Transmit/Receive Clock
Clock
Source
Internal
External
Internal
SCK
Pin Function
SCI does not use the SCK pin
Outputs a clock with frequency
matching the bit rate
Inputs a clock with frequency 16
times the bit rate
Outputs the synchronous clock
External
Inputs the synchronous clock
Rev. 4.00, 03/04, page 373 of 660