HD6417706 Datasheet, PDF (310/709 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

CKIO
A25 to A0
D31 to D0
Transfer source
address
Transfer destination
address
DACKn
Data read cycle
Data write cycle
(1st cycle)
(2nd cycle)
Note: Transfer between external memories, DACK output in a read cycle DACK output timing
is the same as that of .
Figure 9.6 Example of DMA Transfer Timing in the Direct Address Mode
in the Dual Address Mode
(Transfer Source: Ordinary Memory, Transfer Destination: Ordinary Memory)
Rev. 4.00, 03/04, page 264 of 660