HD6417706 Datasheet, PDF (523/709 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

Bit
Bit Name Initial Value R/W Description
5
SCP2MD1 0
R/W SCP2 Mode
4
SCP2MD0 0
R/W 00: Transmit data output 1 (TxD2)
Receive data input 1 (RxD2)
01: General output (SCPT[2] output pin)
Receive data input 1 (RxD2)
10: SCPT[2] input pin pull-up (input pin)
Transmit data output 1 (TxD2)
11: General input (SCPT[2] input pin)
Transmit data output 1 (TxD2)
Note: There is no combination of simultaneous I/O
of SCPT[2] because one bit (SCP2DT) is
accessed using two pins of TxD2 and RxD2.
When the port input is set (bit SCPnMD1 is set to 1)
and when the TE bit in SCSCR is set to 1, the TxD1
pin is in the output state. When the TE bit is
cleared to 0, the TxD2 pin is in the high-impedance
state.
3
SCP1MD1 1
R/W SCP1 Mode
2
SCP1MD0 0
R/W 00: Other function (See table 17.1)
01: Port output
10: Port input (Pull-up MOS: on)
11: Port input (Pull-up MOS: off)
1
SCP0MD1 0
R/W SCP0 Mode
0
SCP0MD0 0
R/W 00: Transmit data output 0 (TxD0)
Receive data input 0 (RxD0)
01: General output (SCPT[0] output pin)
Receive data input 0 (RxD0)
10: SCPT[0] input pin pull-up (input pin)
Transmit data output 0 (TxD0)
11: General input (SCPT[0] input pin)
Transmit data output 0 (TxD0)
Note: There is no combination of simultaneous I/O
of SCPT[0] because one bit (SCP0DT) is
accessed using two pins of TxD0 and RxD0.
When the port input is set (bit SCPnMD1 is set to 1)
and when the TE bit in SCSCR is set to 1, the TxD0
pin is in the output state. When the TE bit is
cleared to 0, the TxD0 pin is in the high-impedance
state.
Rev. 4.00, 03/04, page 477 of 660