HD6417706 Datasheet, PDF (378/709 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

13.3.8 Year Counter (RYRCNT)
The year counter (RYRCNT) is an 8-bit read/write register used for setting/counting in the BCD-
coded year section of the RTC. The least significant 2 digits of the western calendar year are
displayed. The count operation is performed by a carry for each year of the month counter.
The range for year can be set is 00 to 99 (decimal). Errant operation will result if any other value
is set. Carry out write processing after halting the count operation with the START bit in RCR2 or
using a carry flag.
RYRCNT is not initialized by a power-on reset or manual reset, or in standby mode.
Leap years are recognized by dividing the year counter value by 4 and obtaining a fractional result
of 0.
Bit
7 to 4
3 to 0
Bit Name

Initial Value R/W

R/W


R/W
Description
Counter for 10-unit of year in the BCD-code.
The range can be set from 0 to 9 (decimal).
Counter for 1-unit of year in the BCD-code.
The range can be set from 0 to 9 (decimal).
13.3.9 Second Alarm Register (RSECAR)
The second alarm register (RSECAR) is an 8-bit read/write register, and an alarm register
corresponding to the BCD-coded second section counter RSECCNT of the RTC. When the ENB
bit is set to 1, a comparison with the RSECCNT value is performed. From among the
RSECAR/RMINAR/RHRAR/RWKAR/RDAYAR/RMONAR registers, the counter and alarm
register comparison is performed only on those with ENB bits set to 1, and if each of those
coincide, an RTC alarm interrupt is generated.
The range of second can be set is 00 to 59 (decimal). Errant operation will result if any other value
is set.
The ENB bit in RSECAR is initialized to 0 by a power-on reset. The remaining RSECAR fields
are not initialized by a power-on reset or manual reset, or in standby mode.
Rev. 4.00, 03/04, page 332 of 660