HD6417706 Datasheet, PDF(583/709 Page) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

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HD6417706 Datasheet, PDF (583/709 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

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â¢ Canceling Software Standby Mode

Standby mode is canceled by an interrupt (NMI, IRQ*1, IRL*1, or on-chip supporting module)*2

or a reset.

Canceling with an Interrupt: The on-chip WDT can be used for hot starts. When the chip detects

an NMI, IRL*1, IRQ*1, or on-chip supporting module (except the interval timer)*2 interrupt, the

clock will be supplied to the entire chip and software standby mode canceled after the time set in

the WDT's timer control/status register has elapsed. The STATUS1 and STATUS0 pins both go

low. Interrupt processing then begins and a code indicating the interrupt source is set in the

INTEVT and INTEVT2 registers. After branching to the interrupt processing routine occurs, clear

the STBY bit in the STBCR register. The WTCNT stops automatically. If the STBY bit is not

cleared, WTCNT continues operation and transits to the standby mode*3 when it reaches H'80.

This function prevents the data from being destroyed due to a rising voltage under an unstable

power supply. Interrupts are accepted during software standby mode even when the BL bit in the

SR register is 1. If necessary, save SPC and SSR in the stack before executing the SLEEP

instruction. Immediately after an interrupt is detected, the phase of the clock output of the CKIO

pin may be unstable, until the processor starts interrupt processing. (The canceling condition is

that the IRL3 to IRL0 level is higher than the mask level in the I3 to I0 bits in the SR register.)

Notes: 1. Software Standby mode can be canceled using IRL3 to IRL0 or IRQ4 to IRQ0.

2. Software standby mode can be canceled with an RTC or TMU (only when running on

the RTC clock) interrupt.

3. Standby mode should be canceled by power-on resets. Operations at manual resets or

during interrupt input are not guaranted.

WTCNT value

Interrupt

request

WDT overflow and branch to

interrupt handling routine

Crystal oscillator settling

time and PLL synchronization

time

Clear bit STBCR.STBY before

WTCNT reaches H'80. When

STBCR.STBY is cleared, WTCNT

halts automatically.

H'FF

H'80

Time

Figure 22.1 Canceling Software Standby Mode with STBCR.STBY

Rev. 4.00, 03/04, page 537 of 660

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