HD6417706 Datasheet, PDF (531/709 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

18.5 Port E
Port E is an 8-bit I/O port with the pin configuration shown in figure 18.5. Each pin has an input
pull-up MOS, which is controlled by Port E Control Register (PECR) in PFC.
Port E
PTE7 (I/O) /
(output)
PTE6 (I/O) / TCLK (I/O)
PTE5 (I/O) / STATUS1 (output)
PTE4 (I/O) / STATUS0 (output)
PTE3 (I/O) / DRAK1 (output)
PTE2 (I/O) / DRAK0 (output)
PTE1 (I/O) /
(output)
PTE0 (I/O) /
(output)
Figure 18.5 Port E
18.5.1 Register Description
Port E has the following register. Refer to section 23, List of Registers, for more details of the
addresses and access sizes.
• Port E data register (PEDR)
18.5.2 Port E Data Register (PEDR)
Port E data register (PEDR) is an 8-bit read/write register that stores data for pins PTE7 to PTE0.
PE7DT to PE0DT bit corresponds to PTE7 to PTE0 pin. When the pin function is general output
port, if the port is read the value of the corresponding PEDR bit is returned directly. When the
function is general input port, if the port is read the corresponding pin level is read.
PEDR is initialized to H'00 by a power-on reset, after which the general input port function (pull-
up MOS on) is set as the initial pin function, and the corresponding pin levels are read. It retains
its previous value in standby mode and sleep mode, and in a manual reset.
Rev. 4.00, 03/04, page 485 of 660