HD6417706 Datasheet, PDF (16/709 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

Item
17.1.7 Port G Control
Register (PGCR)
Page
472
473
Revision (See Manual for Details)
Bit table amended
Bit
Bit Name Initial Value
11
PG5MD1 1
10
PG5MD0 0
9
PG4MD1 1/0
8
PG4MD0 0
7
PG3MD1 1/0
6
PG3MD0 0
5
PG2MD1 1/0
4
PG2MD0 0
3
PG1MD1 1/0
2
PG1MD0 0
Bit
Bit Name Initial Value
1
PG0MD1 1/0
0
PG0MD0 0
18.5.2 Port E Data Register 485
(PEDR)
19.3.2 A/D Control/Status 499
Register (ADCSR)
500
Description amended
PEDR is initialized to H'00 by a power-on reset, after which the
general input port function (pull-up MOS on) is set as the initial pin
function, and the corresponding pin levels are read. It retains its
previous value in standby mode and sleep mode, and in a manual
reset.
Bit 7 R/W amended
(Before) R/(W)* → (After) R/(W)*¹
Bit 4 description amended
MULTI
0
0
1
1
SCN
0
1
0
1
:Single mode
:Single mode
:Multi mode
:Scan mode
Note *2 added
Bit 3 Clock Select
0: Conversion time = 536 states (maximum)
1: Conversion time = 266 states (maximum)*²
Notes: 1. Only 0 can be written to clear the flag.
2 The CKS value should be set so that the A/D conversion
time is 16 µs (minimum).
Rev. 4.00, 03/04, page xvi of xlvi