HD6417706 Datasheet, PDF (35/709 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

Figure 8.38 Dynamic Bus Sizing Timing for PCMCIA I/O Card Interface ...............................238
Figure 8.39 Waits between Access Cycles .................................................................................239
Figure 8.40 Pins A25 to A0 Pull-Up Timing ..............................................................................240
Figure 8.41 Pins D31 to D0 Pull-Up Timing (Read Cycle) ........................................................241
Figure 8.42 Pins D31 to D0 Pull-Up Timing (Write Cycle) .......................................................241
Section 9 Direct Memory Access Controller (DMAC)
Figure 9.1 DMAC Block Diagram..............................................................................................244
Figure 9.2 DMAC Transfer Flowchart .......................................................................................256
Figure 9.3 Round-Robin Mode ...................................................................................................260
Figure 9.4 Changes in Channel Priority in Round-Robin Mode.................................................261
Figure 9.5 Operation in the Direct Address Mode in the Dual Address Mode ...........................263
Figure 9.6 Example of DMA Transfer Timing in the Direct Address Mode
in the Dual Address Mode (Transfer Source: Ordinary Memory,
Transfer Destination: Ordinary Memory) .................................................................264
Figure 9.7 Example of DMA Transfer Timing in the Direct Address Mode
in the Dual Address Mode (16-byte Transfer, Transfer Source:
Ordinary Memory, Transfer Destination: Ordinary Memory) ..................................265
Figure 9.8 Example of DMA Transfer Timing in the Direct Address Mode
in the Dual Address Mode (16-byte Transfer, Transfer Source:
Synchronous DRAM, Transfer Destination: Ordinary Memory)..............................265
Figure 9.9 Operation in the Indirect Address mode in the Dual Address Mode
(When the External Memory Space has a 16-bit Width) ..........................................267
Figure 9.10 Example of Transfer Timing in the Indirect Address Mode
in the Dual Address Mode.......................................................................................268
Figure 9.11 Data Flow in the Single Address Mode...................................................................269
Figure 9.12 Example of DMA Transfer Timing in the Single Address Mode............................270
Figure 9.13 Example of DMA Transfer Timing in the Single Address Mode
(16- Byte Transfer, External Memory Space (Ordinary Memory) ->
External Device with DACK) .................................................................................271
Figure 9.14 DMA Transfer Example in the Cycle-Steal Mode ..................................................271
Figure 9.15 DMA Transfer Example in the Burst Mode ............................................................272
Figure 9.16 Bus State when Multiple Channels are Operating
(Priority Level is Round-robin Mode) ......................................................................274
Figure 9.17 Cycle-Steal Mode, Level Input (CPU Access: 2 Cycles) ........................................276
Figure 9.18 Cycle-Steal Mode, Level Input (CPU Access: 3 Cycles) ........................................276
Figure 9.19 Cycle-Steal Mode, Level input (CPU Access: 2 Cycles, DMA RD Access:
4 Cycles) ..................................................................................................................276
Figure 9.20 Cycle-Steal Mode, Level input (CPU Access: 2 Cycles, DREQ Input Delayed) ....277
Figure 9.21 Cycle-Steal Mode, Edge input (CPU Access: 2 Cycles) .........................................277
Figure 9.22 Burst Mode, Level Input..........................................................................................277
Figure 9.23 Burst Mode, Edge Input ..........................................................................................278
Figure 9.24 Source Address Reload Function Diagram..............................................................278
Rev. 4.00, 03/04, page xxxv of xlvi