HD6417706 Datasheet, PDF (278/709 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

Memory Card Interface Basic Timing: Figure 8.32 shows the basic timing for the PCMCIA IC
memory card interface. When physical space areas 5 and 6 are designated as PCMCIA interface
areas, bus accesses are automatically performed as IC memory card interface accesses.
With a high external bus frequency (CKIO), the setup and hold times for the address (A24 to A0),
card enable (CS5, CE2A, CS6, CE2B), and write data (D15 to D0) in a write cycle, become
insufficient with respect to RD and WR (the WE pin in this LSI). This LSI provides for this by
enabling setup and hold times to be set for physical space areas 5 and 6 in the PCR register. Also,
software waits by means of a WCR2 register setting and hardware waits by means of the WAIT
pin can be inserted in the same way as for the basic interface. Figure 8.33 shows the PCMCIA
memory bus wait timing.
CKIO
Tpcm1
Tpcm2
A25 to A0
RD/
(read)
D15 to D0
(read)
(write)
D15 to D0
(write)
Figure 8.32 Basic Timing for PCMCIA Memory Card Interface
Rev. 4.00, 03/04, page 232 of 660