HD6417706 Datasheet, PDF (457/709 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

Table 15.5 Examples of SCBRR Settings for Bit Rate B (Bit/s) (n = 0)
7.1424
N Error
0 0.00
10.00
N Error
1 30.00
φ (MHz) (9600 Bits/s)
10.7136
13.00
14.2848
N Error N Error N Error
1 25.00 1 8.99 1 0.00
16.00
N Error
1 12.01
18.00
N Error
2 15.99
Table 15.6 Maximum Bit Rates for Frequencies (Smart Card Interface Mode)
Pφ (MHz)
7.1424
10.00
10.7136
13.00
14.2848
16.00
18.00
Maximum Bit Rate (Bit/s)
9600
13441
14400
17473
19200
21505
24194
N
n
0
0
0
0
0
0
0
0
0
0
0
0
0
0
The bit rate error is found as follows:
Error
(%)
=
(
1488
×
Pφ
2^2n–1 × B
×
(N
+
1)
×
10⁶
–
1)
×
100
Table 15.5 shows example settings of SCBRR, and table 15.6 shows the maximum bit rate for
each frequency.
Table 15.7 shows the relationship between transmit/receive clock register set values and output
states on the smart card interface.
Rev. 4.00, 03/04, page 411 of 660