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HD6417706 Datasheet, PDF (592/709 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series
CKIO
CA
4-5-62
STATUS
Standby*2
Normal*3
Standby*2
Undefined
Reset*1
WDT operation
0 to 10 Bcyc*4
2 Rcyc or more*5
Notes:
1. Reset:
2. Standby:
3. Normal:
4. Bcyc:
5. Rcyc:
HH (STATUS1 high, STATUS0 high)
LH (STATUS1 low, STATUS0 high)
LL (STATUS1 low, STATUS0 low)
Bus clock cycle
EXTAL2 (32.768 kHz) cycle
Figure 22.11 Hardware Standby Mode Timing
(When CA Goes Low during WDT Operation on Standby Mode Cancellation)
Rev. 4.00, 03/04, page 546 of 660