HD6417706 Datasheet, PDF (382/709 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

13.3.13 Date Alarm Register (RDAYAR)
The date alarm register (RDAYAR) is an 8-bit read/write register, and an alarm register
corresponding to the BCD-coded date section counter RDAYCNT of the RTC. When the ENB bit
is set to 1, a comparison with the RDAYCNT value is performed. From among the registers
RSECAR, RMINAR, RHRAR, RWKAR, RDAYAR, RMONAR, the counter and alarm register
comparison is performed only on those with ENB bits set to 1, and if each of those coincide, an
RTC alarm interrupt is generated.
The range of date can be set 01 to 31 (decimal). Errant operation will result if any other value is
set. The RDAYCNT range that can be set changes with some months and in leap years. Please
confirm the correct setting.
The ENB bit in RDAYAR is initialized by a power-on reset. The remaining RDAYAR fields are
not initialized by a power-on reset or manual reset, or in standby mode.
Bit
7
6
5, 4
3 to 0
Bit Name Initial Value R/W Description
ENB
0
R/W Date Alarm Enable
0: No compared
1: Compared

0
R Always read as 0.


R/W Setting value for 10-unit of date alarm in the BCD-code.
The range can be set from 0 to 3 (decimal).


R/W Setting value for 1-unit of date alarm in the BCD-code.
The range can be set from 0 to 9 (decimal).
Rev. 4.00, 03/04, page 336 of 660