HD6417706 Datasheet, PDF (331/709 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

9.5.3 Operation
• Period Count Operation
When an internal clock is selected with the CKS1 and CKS0 bits of the CMCSR register and the
STR bit of the CMSTR is set to 1, the CMCNT begins incrementing with the selected clock. When
the CMCNT counter value matches that of the CMCOR, the CMCNT counter is cleared to H'0000
and the CMF flag of the CMCSR register is set to 1. The CMCNT counter begins counting up
again from H'0000.
Figure 9.27 shows the compare match counter operation.
CMCNT value
CMCOR
Counter cleared by
CMCOR compare match
H'0000
Time
Figure 9.27 Counter Operation
• CMCNT Count Timing
One of four clocks (Pφ/4, Pφ/8, Pφ/16, Pφ/64) obtained by dividing the the system clock (Pφ) can
be selected by the CKS1 and CKS0 bits of the CMCSR. Figure 9.28 shows the timing.
CK
Internal clock
CMCNT0 input
clock
CMCNT0
N-1
N
N+1
Figure 9.28 Count Timing
Rev. 4.00, 03/04, page 285 of 660