HD6417706 Datasheet, PDF (69/709 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

2.3.2 Addressing Modes
Addressing modes and effective address calculation methods are shown in table 2.2.
Table 2.2 Addressing Modes and Effective Addresses
Addressing
Mode
Register
direct
Register
indirect
Instruction
Format Effective Address Calculation Method
Calculation Formula
Rn
Effective address is register Rn. (Operand is —
register Rn contents.)
@Rn
Effective address is register Rn contents. Rn
Rn
Rn
Register
indirect with
post-
increment
@Rn+
Register
indirect with
pre-
decrement
@–Rn
Effective address is register Rn contents. A
constant is added to Rn after instruction
execution: 1 for a byte operand, 2 for a word
operand, 4 for a longword operand.
Rn
Rn
Rn + 1/2/4 ₊
Rn
After instruction
execution
Byte: Rn + 1 → Rn
Word: Rn + 2 → Rn
Longword: Rn + 4 →
Rn
1/2/4
Effective address is register Rn contents, Byte: Rn – 1 → Rn
decremented by a constant beforehand: 1 for _{Word: Rn – 2 → Rn}
a byte operand, 2 for a word operand, 4 for a
longword operand.
Longword: Rn – 4 →
Rn
Rn
(Instruction executed
Rn – 1/2/4 _–
Rn – 1/2/4
with Rn after
calculation)
1/2/4
Rev. 4.00, 03/04, page 23 of 660