HD6417706 Datasheet, PDF (598/709 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

Notes: 1. Modules:
CCN: Cache controller
UBC: User break controller
CPG: Clock pulse generator BSC: Bus state controller
RTC: Realtime clock
INTC: Interrupt controller
TMU: Timer unit
SCI: Serial communication interface
2. Internal buses:
L: CPU, CCN, cache, and TLB connected
I: BSC, cache, DMAC, INTC, CPG, and H-UDI connected
P: BSC and peripheral modules (RTC, TMU, SCI, SCIF, A/D, D/A, DMAC, ports,
CMT) connected
3. The access size shown is for control register access (read/write). An incorrect result
will be obtained if a different size from that shown is used for access.
4. With 16-bit access, it is not possible to read data in two registers simultaneously.
5. With 32-bit access, it is not possible to read data in the register at [accessed address +
2] simultaneously.
Rev. 4.00, 03/04, page 552 of 660