HD6417706 Datasheet, PDF (629/709 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

24.3.3 AC Bus Timing
Table 24.7 Bus Timing
(Clock Modes 0/1/2/7)
Item
Symbol Min Max Unit Figure
Address delay time
tAD
Address setup time
tAS
1.5 12 ns 24.16 to 24.36, 24.39 to 24.46
0 — ns 24.16 to 24.18
Address hold time
BS delay time
CS delay time 1
CS delay time 2
CS delay time 3
Read/write delay time
tAH
tBSD
tCSD1
tCSD2
tCSD3
tRWD
4 — ns 24.16 to 24.21
— 10 ns 24.16 to 24.36, 24.40 to 24.46
— 10 ns 24.16 to 24.21, 24.40 to 24.46
— 10 ns 24.16 to 24.21
1.5 10 ns 24.24 to 24.39
1.5 10 ns 24.16 to 24.46
Read/write hold time
Read strobe delay time
Read data setup time 1
tRWH
tRSD
tRDS1
0 — ns 24.16 to 24.21
— 10 ns 24.16 to 24.21 24.40 to 24.43
6 — ns 24.16 to 24.21, 24.40 to 24.46
Read data setup time 2
Read data hold time 1
Read data hold time 2
tRDS2
tRDH1
tRDH2
5 — ns 24.22 to 24.25, 24.30 to 24.33
0 — ns 24.16 to 24.21, 24.40 to 24.46
2 — ns 24.22 to 24.25, 24.30 to 24.33
Write enable delay time tWED
Write data delay time 1 tWDD1
— 10 ns 24.16 to 22.18, 24.40 to 24.41
— 12 ns 24.16 to 24.18, 24.40 to 24.41, 24.44 to
24.46
Write data delay time 2 tWDD2
Write data hold time 1 tWDH1
1.5 12 ns 24.20 to 24.29
1.5 — ns 24.16 to 24.18, 24.40 to 24.41, 24.44 to
24.46
Write data hold time 2
Write data hold time 3
Write data hold time 4
WAIT setup time
tWDH2
tWDH3
tWDH4
tWTS
1.5 — ns 24.26 to 24.29
2 — ns 24.16 to 24.18
2 — ns 24.40 to 24.41, 24.44 to 24.46
5 — ns 24.17 to 24.21, 24.41, 24.43, 24.45,
24.46
WAIT hold time
tWTH
0 — ns 24.17 to 24.21, 24.41, 24.43, 24.45,
24.46
RAS delay time
CAS delay time
DQM delay time
tRASD
tCASD
tDQMD
1.5 10 ns 24.22 to 24.39
1.5 10 ns 24.22 to 24.39
1.5 10 ns 24.22 to 24.36
Rev. 4.00, 03/04, page 583 of 660