HD6417706 Datasheet, PDF (160/709 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

6.3.2 IRQ Interrupt
IRQ interrupts are input by priority from pins IRQ0 to IRQ5 with a level or an edge. The priority
level can be set by priority setting registers C to D (IPRC to IPRD) in a range from levels 0 to 15.
When using edge-sensing for IRQ interrupts, clear the interrupt source by having software read 1
from the corresponding bit in IRR0, then write 0 to the bit.
When the ICR1 register is rewritten, IRQ interrupts may be mistakenly detected, depending on the
pin states. To prevent this, rewrite the register while interrupts are masked, then release the mask
after clearing the illegal interrupt by writing 0 to interrupt request register 0 (IRR0).
It is necessary for an edge input interrupt detection to input a pulse width more than two-cycle
width by peripheral clock (Pφ) basis.
In level detection, keep the level until the CPU accepts an interrupt and starts the interrupt
processing.
The interrupt mask bits (I3 to I0) of the status register (SR) are not affected by IRQ interrupt
processing.
Interrupts IRQ4 to IRQ0 can wake the chip up from the software standby state when the relevant
interrupt level is higher than I3 to I0 in the SR register (but only when the RTC 32-kHz oscillator
is used).
Notes: When the IRQ is used in edge sensitive, pay attention to the following:
1. If an IRQ edge is input immediately before the CPU enters standby mode (the period
between the SLEEP instruction executed by the CPU to high level of STATUS0), an
interrupt may not be detected. In this case, when an IRQ edge is input again after
STATUS0 becomes high level, an interrupt is detected.
2. If an IRQ edge is input while the frequency is changed by the FRQCR STC bit (when
the WDT is counting), an interrupt may not be detected. In this case, when an IRQ
edge is input again after the WDT halts counting, an interrupt is detected.
Rev. 4.00, 03/04, page 114 of 660