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| HD6417706 Datasheet, PDF (651/709 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series | |||
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;;Tp
Tpw
Tr
Trw
Tc1
Tc2
Tc3
CKIO
tAD
A25 to A16
tAD
A12 or A11
A15 to A0
tCSD3
Row address
tAD
tAD
Row
address
tAD
tAD
tAD
Row
address
Write command
Column address
RD/
tRWD
tRWD
tRWD
tRASD
tRASD
tRASD
tRASD
tCASD
DQMxx
tDQMD
tDQMD
tWDD2
Td4
tAD
tAD
tAD
tCSD3
tRWD
tCASD
tDQMD
tWDD2
D31 to D0
tBSD
tBSD
CKE
DACKn
(HIGH)
tDAKD1
tDAKD1
Figure 24.36 Synchronous DRAM Burst Write Bus Cycle
(RAS Down, Different Row Address, TPC = 1, RCD = 1)
Rev. 4.00, 03/04, page 605 of 660
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