HD6417706 Datasheet, PDF (186/709 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

7.2.5 Break Address Mask Register B (BAMRB)
BAMRB is a 32-bit read/write register. BAMRB specifies bits masked in the break address
specified by BARB.
Bit
31 to 0
Bit Name Initial Value
BAMB31 to All 0
BAMB0
Note: n = 31 to 0
R/W Description
R/W Break Address Mask
Specifies bits masked in the channel B break
address bits specified by BARB (BAB31 to BAB0).
0: Break address BABn of channel B is included in
the break condition
1: Break address BABn of channel B is masked and
is not included in the break condition
7.2.6 Break Data Register B (BDRB)
BDRB is a 32-bit read/write register.
Bit
31 to 0
Bit Name
BDB31 to
BDB0
Initial Value R/W Description
All 0
R/W Break Data Bit
7.2.7 Break Data Mask Register B (BDMRB)
BDMRB is a 32-bit read/write register. BDMRB specifies bits masked in the break data specified
by BDRB.
Bit
Bit Name Initial Value R/W Description
31 to 0 BDMB31 to All 0
BDMB0
R/W Break Data Mask
0: Break data BDBn of channel B is included in the
break condition
1: Break data BDBn of channel B is masked and is
not included in the break condition
Notes: n = 31 to 0
Specify an operand size when including the value of the data bus in the break condition.
When a byte size is selected as a break condition, the break data must be set in bits 15 to 8
in BDRB for an even break address and bits 7 to 0 for an odd break address.
Rev. 4.00, 03/04, page 140 of 660