HD6417706 Datasheet, PDF (501/709 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

4. If the RIE bit in SCSCR2 is set to 1 when the RDF or DR flag changes to 1, a receive-FIFO-
data-full interrupt (RXI) request is generated.
If the RIE bit in SCSCR2 is set to 1 when the ER flag changes to 1, a receive-error interrupt
(ERI) request is generated.
If the RIE bit in SCSCR2 is set to 1 when the BRK flag changes to 1, a break reception
interrupt (BRI) request is generated.
Figure 16.11 shows an example of the operation for reception.
1
Serial
data
Start
bit
Data
Parity Stop Start
bit bit bit
Data
Parity Stop
bit bit
0 D0 D1
D ₇ 0/1 1
0 D0 D1
D ₇ 0/1 1
1
Idling
(marking)
RDF
FER
RXI interrupt
request
One frame
Data read and RDF
flag read as 1 then
cleared to 0 by
RXI interrupt handler
ERI interrupt
request generated
by receive error
Figure 16.11 Example of SCIF Receive Operation
(Example with 8-Bit Data, Parity, One Stop Bit)
5. When modem control is enabled, the RTS2 signal is output when SCFRDR2 is empty. When
RTS2 is 0, reception is possible. When RTS2 is 1, this indicates that SCFRDR2 is full and
reception is not possible.
Figure 16.12 shows an example of the operation when modem control is used.
Serial
data
RXD2
Start
bit
0 D0 D1 D2
Parity bit
D7 0/1 1
Start
0
Figure 16.12 Example of Operation Using Modem Control (RTS2)
Rev. 4.00, 03/04, page 455 of 660