HD6417706 Datasheet, PDF (281/709 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

CKIO
Tpcm0 Tpcm1 Tpcm1wTpcm1wTpcm1w Tpcm2 Tpcm1 Tpcm1w Tpcm2 Tpcm2w
A25 to A4
A3 to A0
RD/
(read)
D15 to D0
(read)
Figure 8.35 Wait Timing for PCMCIA Memory Card Interface Burst Access
When the entire 32-Mbyte memory space is used as IC memory card interface space, the common
memory/attribute memory switching signal REG is generated using a port, etc. If 16-Mbytes or
less of memory space is sufficient, using 16 Mbytes of memory space as common memory space
and 16 Mbytes as attribute memory space enables the A24 pin to be used for the REG signal.
I/O Card Interface Timing: Figures 8.36 and 8.37 show the timing for the PCMCIA I/O card
interface.
Switching between the I/O card interface and the IC memory card interface is performed
according to the accessed address. When PCMCIA is designed for physical space area 5, the bus
access is automatically performed as an I/O card interface access when a physical address from
H'16000000 to H'17FFFFFF is accessed. When PCMCIA is designated for physical space area 6,
the bus access is automatically performed as an I/O card interface access when a physical address
from H'1A000000 to H'1BFFFFFF is accessed.
When accessing a PCMCIA I/O card, the access should be performed using a non-cacheable area
in virtual space (P2 or P3 space) or an area specified as non-cacheable by the MMU.
Rev. 4.00, 03/04, page 235 of 660