HD6417706 Datasheet, PDF (134/709 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

Bit
31 to 12
11 to 0
Bit Name


Initial Value R/W
All 0
R

R/W
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
12-bit interrupt exception code or a code indicating
the interrupt priority
4.2.3 Interrupt Event Register 2 (INTEVT2)
The interrupt event register 2 (INTEVT2) contains a 12-bit exception code. The exception code set
in INTEVT2 is that for an interrupt request. The exception code is set automatically by hardware
when an exception occurs.
Bit
31 to 12
11 to 0
Bit Name


Initial Value R/W
All 0
R

R/W
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
12-bit exception code
4.2.4 TRAPA Exception Register (TRA)
The TRAPA exception register (TRA) contains 8-bit immediate data (imm) for the TRAPA
instruction. TRA is set automatically by hardware when a TRAPA instruction is executed. TRA
can also be modified by software.
Bit
31 to 10
9 to 2
1, 0
Bit Name

imm

Initial Value R/W
All 0
R

R/W
All 0
R
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
8-bit immediate data
Reserved
These bits are always read as 0. The write value
should always be 0.
Rev. 4.00, 03/04, page 88 of 660