HD6417706 Datasheet, PDF (49/709 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

1.2 Block Diagram
MMU
TLB
CCN
CACHE
BRIDGE
CPU
UBC
AUD
SCI
TMU
RTC
H-UDI
INTC
CPG/WDT
BSC
DMAC
CMT
SCIF
ADC
DAC
External bus
interface
I/O port
Legend
ADC
: A/D converter
AUD
: Advanced user debugger
BSC
: Bus state controller
CACHE : Cache memory
CCN
: Cache memory controller
CMT
: Compare match timer
CPG/WDT : Clock pulse generator/watchdog timer
CPU
: Central processing unit
DAC
: D/A converter
DMAC
H-UDI
INTC
MMU
RTC
SCI
SCIF
TLB
TMU
UBC
: Direct memory access controller
: User debugging interface
: Interrupt controller
: Memory management unit
: Realtime clock
: Serial communication interface (with smart card interface)
: Serial communication interface (with FIFO)
: Address translation buffer
: Timer unit
: User break controller
Figure 1.1 SH7706 Block Diagram
Rev. 4.00, 03/04, page 3 of 660