HD6417706 Datasheet, PDF (334/709 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

Table 9.7 Values in the DMAC after the Fourth Transfer Ends
Items
Address reload on
Address reload off
SAR_2
H'04000080
H'04000090
DAR_2
H'003FFFFC
H'003FFFFC
DMATCR_2
H'0000007C
H'0000007C
Bus right
Released
Held
DMAC operation
Stops
Keeps operating
Interrupt
Not generated
Not generated
Transfer request source flag Executed
clear
Not executed
Notes: 1. An interrupt is generated regardless of whether the address reload function is on or off,
if transfers are executed until the value in DMATCR_2 reaches 0 and the IE bit in
CHCR_2 has been set to 1.
2. The transfer request source flag is cleared regardless of whether the address reload
function is on or off, if transfers are executed until the value in DMATCR_2 reaches 0.
3. Specify the burst mode to use the address reload function. This function may not be
correctly executed in the cycle steal mode.
4. Set the value multiple of four in DMATCR_2 to use the address reload function. This
function may not be correctly executed if other values are specified.
9.6.2
Example of DMA Transfer between External Memory and SCIF Transmitter
(Indirect Address on)
In this example, DMA transfer is performed between the external memory specified with the
indirect address (transfer source) and the SCIF transmitter (transfer destination) using DMAC
channel 3. Table 9.8 shows the transfer conditions and register settings. In addition, the trigger of
the number of transmit FIFO data is set to 1 (TTRG1 = TTRG0 = 1 in SCFCR).
Rev. 4.00, 03/04, page 288 of 660