HD6417706 Datasheet, PDF (504/709 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

6. Receive Data Sampling Timing and Receive Margin
The SCIF operates on a base clock with a frequency of 16 times the transfer rate. In
reception, the SCIF synchronizes internally with the fall of the start bit, which it samples on
the base clock. Receive data is latched at the rising edge of the eighth base clock pulse. The
timing is shown in figure 16.13.
Base clock
Receive
data (RxD2)
Synchro-
nization
sampling
timing
16 clocks
8 clocks
0 1 2 3 4 5 6 7 8 9 10111213 1415 0 1 2 3 4 5 6 7 8 9 10111213 1415 0 1 2 3 4 5
–7.5 clocks +7.5 clocks
Start bit
D0
D1
Data
sampling
timing
Figure 16.13 Receive Data Sampling Timing in Asynchronous Mode
The receive margin in asynchronous mode can therefore be expressed as shown in equation 1.
Equation 1:
M = 0.5 – ¹ – (L – 0.5) F – ^{D – 0.5} (1 + F) × 100%
2N
N
M: Receive margin (%)
N: Ratio of clock frequency to bit rate (N = 16)
D: Clock duty cycle (D = 0 to 1.0)
L: Frame length (L = 9 to 12)
F: Absolute deviation of clock frequency
From equation 1, if F = 0 and D = 0.5, the receive margin is 46.875%, as given by equation 2.
Equation 2:
When D = 0.5 and F = 0:
M = (0.5 – 1/(2 × 16)) × 100%
= 46.875%
This is a theoretical value. A reasonable margin to allow in system designs is 20% to 30%.
Rev. 4.00, 03/04, page 458 of 660