HD6417706 Datasheet, PDF (24/709 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

7.2.2 Break Address Mask Register A (BAMRA)........................................................ 138
7.2.3 Break Bus Cycle Register A (BBRA).................................................................. 138
7.2.4 Break Address Register B (BARB) ..................................................................... 139
7.2.5 Break Address Mask Register B (BAMRB) ........................................................ 140
7.2.6 Break Data Register B (BDRB) ........................................................................... 140
7.2.7 Break Data Mask Register B (BDMRB).............................................................. 140
7.2.8 Break Bus Cycle Register B (BBRB) .................................................................. 141
7.2.9 Break Control Register (BRCR) .......................................................................... 142
7.2.10 Execution Times Break Register (BETR)............................................................ 145
7.2.11 Branch Source Register (BRSR).......................................................................... 146
7.2.12 Branch Destination Register (BRDR).................................................................. 147
7.2.13 Break ASID Register A (BASRA)....................................................................... 147
7.2.14 Break ASID Register B (BASRB) ....................................................................... 148
7.3 Operation .......................................................................................................................... 148
7.3.1 Flow of the User Break Operation ....................................................................... 148
7.3.2 Break on Instruction Fetch Cycle......................................................................... 149
7.3.3 Break by Data Access Cycle................................................................................ 149
7.3.4 Sequential Break .................................................................................................. 150
7.3.5 Value of Saved Program Counter ........................................................................ 150
7.3.6 PC Trace .............................................................................................................. 151
7.3.7 Usage Examples................................................................................................... 153
7.4 Usage Note........................................................................................................................ 156
Section 8 Bus State Controller (BSC) ...............................................................159
8.1 Feature .............................................................................................................................. 159
8.2 Input/Output Pin................................................................................................................ 161
8.3 Area Overview .................................................................................................................. 162
8.3.1 PCMCIA Support ................................................................................................ 165
8.4 Register Description.......................................................................................................... 169
8.4.1 Bus Control Register 1 (BCR1) ........................................................................... 169
8.4.2 Bus Control Register 2 (BCR2) ........................................................................... 172
8.4.3 Wait State Control Register 1 (WCR1)................................................................ 174
8.4.4 Wait State Control Register 2 (WCR2)................................................................ 177
8.4.5 Individual Memory Control Register (MCR) ...................................................... 180
8.4.6 PCMCIA Control Register (PCR)........................................................................ 185
8.4.7 Synchronous DRAM Mode Register (SDMR) .................................................... 188
8.4.8 Refresh Timer Control/Status Register (RTCSR)................................................ 188
8.4.9 Refresh Timer Counter (RTCNT)........................................................................ 191
8.4.10 Refresh Time Constant Register (RTCOR) ......................................................... 191
8.4.11 Refresh Count Register (RFCR) .......................................................................... 192
8.5 Operation .......................................................................................................................... 192
8.5.1 Endian/Access Size and Data Alignment............................................................. 192
8.5.2 Description of Areas ............................................................................................ 197
Rev. 4.00, 03/04, page xxiv of xlvi