HD6417706 Datasheet, PDF (9/709 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

Main Revisions and Additions in this Edition
Item
1.2 Block Diagram
Figure 1.1 Pin Assignment
(TBP-208A)
1.4 Pin Function
Page Revision (See Manual for Details)
4
Figure 1.1 title amended
6 to 12 Package name amended
Number of Pins
FP-176C
TBP-208A
Pin Name
9
2.1.4 Control Registers
18
2.3.2 Addressing Modes
26
Table 2.2 Addressing Modes
and Effective Addresses
2.4.1 Instruction Set
38
Classified by Function
Table 2.7 Logic Operation
Instructions
Description amended
Chip select 0
• Status Register (SR)
Description of bit 29 amended
Register bank bit
Determines the bank of general registers R0 to R7 used in privileged
mode. …
Note amended
Note: For the addressing modes below that use a displacement
(disp), the assembler descriptions in this manual show the value
before scaling (×1, ×2, or ×4) is performed according to the operand
size. This is done to clarify the operation of the LSI. Refer to the
relevant assembler notation rules for the actual assembler
descriptions.
Table 2.7 amended
Instruction
TAS.B @Rn*
Operation
If (Rn) is 0, 1 → T;
1 → MSB of (Rn)*
Code
0100nnnn00011011
Privileged
Mode
Cycles T Bit
—
4
Test
result
Rev. 4.00, 03/04, page ix of xlvi