HD6417706 Datasheet, PDF (190/709 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

Bit
Bit Name Initial Value R/W Description
12
SCMFDB 0
R/W DMAC Condition Match Flag B
When the on-chip DMAC bus cycle condition in the
break conditions set for channel B is satisfied, this
flag is set to 1 (not cleared to 0). In order to clear this
flag, write 0 into this bit.
0: The DMAC cycle condition for channel B does not
match
1: The DMAC cycle condition for channel B matches
11
PCTE
0
R/W PC Trace Enable
Enables PC trace.
0: Disables PC trace
1: Enables PC trace
10
PCBA
0
R/W PC Break Select A (PCBA)
Selects the break timing of the instruction fetch cycle
for channel A as before or after instruction execution.
0: PC break of channel A is set before instruction
execution
1: PC break of channel A is set after instruction
execution
9, 8
—
All 0
R Reserved
These bits are always read as 0. The write value
should always be 0.
7
DBEB
0
R/W Data Break Enable B
Selects whether or not the data bus condition is
included in the break condition of channel B.
0: No data bus condition is included in the condition of
channel B
1: The data bus condition is included in the condition
of channel B
6
PCBB
0
R/W PC Break Select B
Selects the break timing of the instruction fetch cycle
for channel B as before or after instruction execution.
0: PC break of channel B is set before instruction
execution
1: PC break of channel B is set after instruction
execution
5, 4
—
All 0
R Reserved
These bits are always read as 0. The write value
should always be 0.
Rev. 4.00, 03/04, page 144 of 660