HD6417706 Datasheet, PDF (210/709 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

Area Connectable Memory Physical Address
Capacity Access Size
5
Ordinary memory*¹,
H'14000000 to H'15FFFFFF
PCMCIA, burst ROM _{H'16000000 to H'17FFFFFF}
32 Mbytes
32 Mbytes
8, 16, 32*³ *⁶
H'14000000 + H'20000000 × n to Shadow
H'17FFFFFF + H'20000000 × n
n: 1 to 6
6
Ordinary memory*¹,
H'18000000 to H'19FFFFFF
PCMCIA, burst ROM _{H'1A000000 to H'1BFFFFFF}
32 Mbytes 8, 16, 32*³ *⁶
7*⁷ Reserved area
H'18000000 + H'20000000 × n to
H'1BFFFFFF + H'20000000 × n
H'1C000000 + H'20000000 × n
to H'1FFFFFFF + H'20000000 × n
Shadow
n: 1 to 6
n: 0 to 7
Notes: 1. Memory with interface such as SRAM or ROM.
2. Use external pin to specify memory bus width.
3. Use register to specify memory bus width.
4. With synchronous DRAM interfaces, bus width must be 16 or 32 bits.
5. With synchronous DRAM interfaces, bus width must be 16 or 32 bits.
6. With PCMCIA interface, bus width must be 8 or 16 bits.
7. Do not access the reserved area. If the reserved area is accessed, the correct
operation cannot be guaranteed.
8. When the control register in area 1 is not used for address translation by the MMU, set
the top three bits of the logical address to 101 to allocate in the P2 space.
Area 0: H'00000000
Area 1: H'04000000
Area 2: H'08000000
Area 3: H'0C000000
Area 4: H'10000000
Area 5: H'14000000
Area 6: H'18000000
Ordinary memory/
burst ROM
Internal I/O
Ordinary memory/
synchronous DRAM
Ordinary memory/
synchronous DRAM
Ordinary memory
Ordinary memory/
burst ROM/PCMCIA
Ordinary memory/
burst ROM/PCMCIA
The PCMCIA interface is shared
by the memory and I/O card
The PCMCIA interface is shared
by the memory and I/O card
Figure 8.3 Physical Space Allocation
Rev. 4.00, 03/04, page 164 of 660