HD6417706 Datasheet, PDF (297/709 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

Bit
Bit Name Initial Value R/W Description
7
—
0
R
Reserved
6
DS
0
This bit is always read 0. The write value should
always be 0.
(R/W)*² DREQ Select Bit
DS selects the sampling method of the DREQ pin
that is used in external request mode is detection in
low level or at the falling edge.
This bit is only valid in CHCR_0 and CHCR_1.
Writing to this bit is invalid in CHCR_2 and CHCR_3;
0 is read if this bit is read.
In channel 0 and 1, if an on-chip peripheral module is
specified as a transfer request source or an auto
request is specified, specification of this bit is ignored
and detection at the falling edge is fixed except in an
auto-request.
0: DREQ detected in low level
1: DREQ detected at falling edge
5
TM
0
R/W Transmit Mode
TM specifies the bus mode when transferring data.
0: Cycle steal mode
1: Burst mode
4
TS1
0
R/W Transmit Size Bits 1 and 0
3
TS0
0
R/W TS1 and TS0 specify the size of data to be
transferred.
00: Byte size (8 bits)
01: Word size (16 bits)
10: Longword size (32 bits)
11: 16-byte unit (4 longword transfers)
2
IE
0
R/W Interrupt Enable Bit
Setting this bit to 1 generates an interrupt request
when data transfer end (TE = 1) by the count
specified in DMATCR.
0: Interrupt request is not generated even if data
transfer ends by the specified count
1: Interrupt request is generated if data transfer ends
by the specified count
Rev. 4.00, 03/04, page 251 of 660