HD6417706 Datasheet, PDF (74/709 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

Instruction Format
Source
Operand
Destination
Operand
Instruction
Example
nm
format
15
0 mmmm: register nnnn: register
xxxx nnnn mmmm xxxx ^direct
direct
ADD
Rm,Rn
mmmm: register nnnn: register MOV.L
indirect
indirect
Rm,@Rn
mmmm: register
indirect with post-
increment
(multiply-and-
accumulate
operation)
MACH,MACL
MAC.W
@Rm+,@Rn+
nnnn: * register
indirect with post-
increment
(multiply-and-
accumulate
operation)
mmmm: register nnnn: register
indirect with post- direct
increment
MOV.L
@Rm+,Rn
mmmm: register
direct
nnnn: register MOV.L
indirect with pre- Rm,@–Rn
decrement
mmmm: register nnnn: indexed MOV.L
direct
register indirect Rm,@(R0,Rn)
md
format
15
xxxx
0 mmmmdddd:
R0 (register
xxxx mmmm dddd register indirect direct)
with displacement
MOV.B
@(disp,Rm),R
0
nd4
format
15
xxxx
xxxx
nnnn
0 R0 (register direct) nnnndddd:
dddd
register indirect
with
displacement
MOV.B
R0,@(disp,Rn)
Rev. 4.00, 03/04, page 28 of 660