HD6417706 Datasheet, PDF (394/709 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

• Four types of interrupts
Transmit-data-empty, transmit-end, receive-data-full, and receive-error interrupts are requested
independently.
• Saving power
When the SCI is not in use, it can be stopped by halting the clock supply for the saving power.
Figure 14.1 shows a SCI block diagram.
Module data bus
Internal
data bus
RxD0
TxD0
SCK0
SCRDR
SCRSR
SCTDR
SCTSR
SCPCR
SCPDR
SCSSR
SCSCR
SCSMR
Transmit/
receive
control
SCBRR
Baud rate
generator
Parity generation
Parity check
Clock
External clock
Legend
SCRSR: Receive shift register
SCRDR: Receive data register
SCTSR: Transmit shift register
SCTDR: Transmit data register
SCSMR: Serial mode register
SCI
SCSCR: Serial control register
SCSSR: Serial status register
SCBRR: Bit rate register
SCPDR: SC port data register
SCPCR: SC port control register
Figure 14.1 SCI Block Diagram
Pφ
Pφ/4
Pφ/16
Pφ/64
TEI
TXI
RXI
ERI
Rev. 4.00, 03/04, page 348 of 660