HD6417706 Datasheet, PDF (589/709 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

Sleep to Power-On Reset:
CKIO
*¹
Reset
STATUS
Normal*⁴
Sleep*³
*⁶
Reset*³
Normal*4
Notes:
0 to 10 Bcyc*⁵
0 to 30 Bcyc*⁵
1. When the PLL1’s multiplication ratio is changed by a power-on reset, keep
PLL’s oscillation settling time.
2. Reset: HH (STATUS1 high, STATUS0 high)
3. Sleep: HL (STATUS1 high, STATUS0 low)
4. Normal: LL (STATUS1 low, STATUS0 low)
5. Bcyc:
Bus clock cycle
6. Undefined
low during the
Figure 22.8 Sleep to Power-On Reset STATUS Output
Sleep to Manual Reset:
Reset
CKIO
*¹
STATUS Normal*⁴
Sleep*³
Reset*²
Normal*⁴
0 to 80 Bcyc*⁵
0 to 30 Bcyc*⁵
Notes:
1. Keep
2. Reset:
3. Sleep:
4. Normal:
5. Bcyc:
low until STATUS becomes reset.
HH (STATUS1 high, STATUS0 high)
HL (STATUS1 high, STATUS0 low)
LL (STATUS1 low, STATUS0 low)
Bus clock cycle
Figure 22.9 Sleep to Manual Reset STATUS Output
Rev. 4.00, 03/04, page 543 of 660