HD6417706 Datasheet, PDF (149/709 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

Whenever CCR2 bit 8 (W3LOCK) or bit 0 (W2LOCK) is high level the cache is locked. The
locked data will not be overwritten unless W3LOCK bit and W2LOCK bit are reset or the PREF
condition during cache locking mode watches. During cache locking mode, the LRU in table 5.1
will be replaced by tables 5.4 to 5.6.
Table 5.2 Way to be Replaced when Cache Miss Occurs during PREF Instruction
Execution
CL bit W3LOAD W3LOCK W2LOAD W2LOCK Way to be Replaced
0
*
*
*
*
According to LRU (table 5.1)
1
*
0
*
0
According to LRU (table 5.1)
1
*
0
0
1
According to LRU (table 5.4)
1
0
1
*
0
According to LRU (table 5.5)
1
0
1
0
1
According to LRU (table 5.6)
1
0
*
1
1
Way 2
1
1
1
0
*
Way 3
Note: Do not set 1 into W2LOAD and W3LOAD at the same time.
* Don't care
Table 5.3 Way to be Replaced when Cache Miss Occurs during Execution of Instruction
other than PREF Instruction
CL bit W3LOAD W3LOCK W2LOAD W2LOCK Way to be Replaced
0
*
*
*
*
According to LRU (table 5.1)
1
*
0
*
0
According to LRU (table 5.1)
1
*
0
*
1
According to LRU (table 5.4)
1
*
1
*
0
According to LRU (table 5.5)
1
*
1
*
1
According to LRU (table 5.6)
Note: Do not set 1 into W2LOAD and W3LOAD at the same time.
* Don't care
Table 5.4 LRU and Way Replacement (when W2LOCK=1)
LRU (5 to 0)
000000, 000001, 000100, 010100, 100000, 100001, 110000, 110100
000011, 000110, 000111, 001011, 001111, 010110, 011110, 011111
101001, 101011, 111000, 111001, 111011, 111100, 111110, 111111
Way to be Replaced
3
1
0
Rev. 4.00, 03/04, page 103 of 660