HD6417706 Datasheet, PDF (136/709 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

4.3.3 General Exceptions
When the SH7706 encounters any exception condition other than a reset or interrupt request, it
executes the following operations:
1. The contents of the PC and SR are saved in the SPC and SSR, respectively.
2. The BL bit in SR is set to 1, masking any subsequent exceptions.
3. The MD bit in SR is set to 1 to place the SH7706 in privileged mode.
4. The RB bit in SR is set to 1.
5. An encoded value identifying the exception event is written to bits 11 to 0 of the EXPEVT
register.
6. Instruction execution jumps to the vector location designated by either the sum of the vector
base address and offset H'00000400 in the vector table in a TLB miss trap, or by the sum of the
vector base address and offset H'00000100 for exceptions other than TLB miss traps, to invoke
the exception handler.
4.4 Individual Exception Operations
This section describes the conditions for specific exception processing, and the processor
operations.
4.4.1 Resets
• Power-On Reset
 Conditions: RESETP low
 Operations: EXPEVT set to H'000, VBR and SR initialized, branch to PC = H'A0000000.
Initialization sets the VBR register to H'0000000. In SR, the MD, RB and BL bits are set to
1 and the interrupt mask bits (I3 to I0) are set to B'1111. The CPU and on-chip supporting
modules are initialized. For details, refer to section 23, List of Registers. A power-on reset
must always be performed when powering on.
A high level is output from the STATUS0 and STATUS1 pins.
• Manual Reset
 Conditions: RESETM low
 Operations: EXPEVT set to H'020, VBR and SR initialized, branch to PC = H'A0000000.
Initialization sets the VBR register to H'0000000. In SR, the MD, RB, and BL bits are set
to 1 and the interrupt mask bits (I3 to I0) are set to B'1111. The CPU and on-chip
supporting modules are initialized. For details, refer to section 23, List of Registers.
A high level is output from the STATUS0 and STATUS1 pins.
Rev. 4.00, 03/04, page 90 of 660